1. Field of the Invention
The present invention relates to a digital integrated semiconductor circuit having a clock pulse generator supplying two different sequences of clock pulses of the same frequency, in which the two clock pulse sequences supplied by the clock pulse generator have the same operating level and a defined pause is respectively provided between the operating levels of the one clock pulse sequence and the operating levels of the other clock pulse sequence, and more particularly to such an arrangement in which a circuit part is present which can be shifted into the digital initial state by means of a reset pulse and a generator generating the reset pulses is provided, and in which, in addition, a first operating potential, as well as a second operating potential, switched as a reference potential, are provided for the operation of the semiconductor circuit.
2. Description of the Prior Art
A clock pulse generator which is capable of delivering the periodic clock pulses TM and TS of the type mentioned above is described, for example, in the German patent application Ser. No. P 27 13 319.3. In principle, all digital circuit portions which can assume a plurality of stable operating conditions come into consideration as circuit portions which can be shifted into the initial digital condition by means of reset pulses. Counters, shift registers, flip-flop cells and logical gates are of primary concern.
In the known digital integrated semiconductor circuits, the reset pulses are spontaneously generated by means of an appropriate circuit design of the system, for example, in that the system is briefly switched off from the first operating potential U.sub.GG and is again connected thereto. Sometimes, however, it is desirable to trigger a resetting of one or more circuit portions in any desired digital condition of such a system without interrupting the operation of the clock pulse generator and further circuit portions, to which end the generation of a reset pulse is necessary, the reset pulse being clearly discriminated from the remaining signals, particularly also from the two clock pulse sequences TM and TS, the reset pulse being generated, as desired, by means of a switch.